Two charge transfer structures have traditionally been employed to realize a Time Delay and Integration (TDI) signal processing function on a readout integrated circuit (ROIC). These charge transfer structures are the charge coupled device (CCD) and the bucket brigade.
In order to obtain a high charge transfer efficiency (CTE) and a low noise performance, implementations for these charge transfer structures have required nonstandard fabrication processes. Specifically, the high CTE CCD structure typically requires the presence of active poly 1 and poly 2 metal oxide semiconductor (MOS) storage and transfer gates, and is thus not practical for realization in a single poly implementation. The bucket brigade structure typically utilizes a depletion implant to form a charge well and a charge transfer drain.
Unfortunately, process options for forming depletion implants, as well as multiple layers of active polygate structures, are becoming less common, and are generally not available in advanced sub-micron commercial CMOS technologies.
In general, both of the CCD and bucket brigade structures operate under the principal that a series of charge wells are created within the structure. Charge can be introduced into one or more of these wells. This charge can then be transferred through the structure from one charge well to another. This process provides the ability to move a quantity of charge, often referred to as a charge packet, from one location in an integrated circuit to another location. These structures therefore provide an ability to multiplex a large number of charge wells into a single output stage. In addition, multiple charge wells can be combined into a single well. Of particular interest to the teachings of this invention, this process can be employed to perform time delay and integration (TDI) signal processing function for infrared and other types of sensor arrays.
Reference in regard to the foregoing can be had, by example, to a publication entitled "Charge Coupled Devices and Systems", M. V. Howes and D. V. Morgan, John Wiley & Sons, 1979. Reference may also be had to U.S. Pat. No. 5,453,781, issued on Sep. 26, 1995 to John T. Stein, and entitled "Apparatus and Method for Minimizing Velocity-Mismatch MTF Degradation in TDI Systems" for a description of one type of TDI system which can be constructed using CCD technology. In general, a TDI system operates to synchronize the operation of the imaging system with a motion of a feature of interest in a scene viewed by the imaging system. By thereby increasing the charge integration time, a beneficial increase in both the sensitivity and the signal-to-noise ratio of the imaging system is achieved.
FIG. 1 and FIGS. 2A-2D (collectively referred to as FIG. 2) show timing and schematic diagrams, respectively, for a conventional four phase CCD structure, and are useful in explaining the operation of a four phase double poly CCD. Four wave forms are shown in FIG. 1, each corresponding to one of clock signal phases P1 through P4. For the purposes of explanation a P-channel 4-phase 2-poly CCD device is described. However, it is well known that the complementary configuration using N-channel devices can also be realized. Clocks P1 through P4 are shown such that the upper rail of the clock voltage represents zero volts, and the lower rail represents a negative voltage which is assumed to be sufficient for depleting the metal oxide semiconductor (MOS) surface that underlies the gate to which the clock is applied.
For the purposes of this discussion the process of biasing the MOS gate to form the depletion region or charge well is referred to as turning the gate "on", and the process of biasing the MOS gate to collapse the depletion region is referred to as turning the gate "off". At time location "A" shown in FIG. 1, the P1 and P4 gates are on or depleted and the P2 and P3 gates are off. It can be seen from FIG. 1 that the depleted clock phase shifts in time from the P1, P2, P3 through the P4 clocks.
Generally, in such a 4-phase CCD structure two of the 4-phases are designed as the primary charge storage or transfer wells. FIG. 2 shows that the P1 and P3 gates represent the primary charge transfer gates. The remaining two-phase gates are provided to aid the charge transfer process and direction control, and the P2 and P4 gates represent these transfer gates. The CCD gates P1 and P3 would generally be implemented using a poly-1 layer, and the gates P2 and P4 would be implemented using a poly-2 layer (i.e., a two poly-process). For the purposes of discussing the functionality of the CCD structure it is assumed that the initial charge injection occurs into the P1 primary charge transfer well. However, it should be recognized that the P3 gate can also serve this function.
The first step in the operation of the CCD circuit is the formation of a charge well under the P1 gate. This is accomplished by biasing the poly-1 P1 gate such that the MOS gate is depleted or on. This forms the charge well which, to a first order, is capable of holding a charge equal to the depleted surface potential delta multiplied by the well to gate capacitance. Charge is introduced into the first phase charge well by one of a number of means, and is generally performed by a charge injection circuit stage (not shown). FIG. 1 illustrates the timing relationship between clock phases P1, P2, P3 and P4 at time condition "A" when charge can be transferred into the P1 charge storage well. Charge is then transferred from the P1 primary storage well to the P3 primary store well. The timing for this process is shown in FIG. 1.
The schematic and surface potential diagrams for the charge transfer process is illustrated in FIG. 2. Specifically, FIGS. 2A-2D correspond to the four time points A-D shown in FIG. 1. At time point A (FIG. 2A) the gates P4 and P1 are biased on. At time point B (FIG. 2B) the gates P1 and P2 are biased on, while at time point C (FIG. 2C) the gates P2 and P3 are biased on, and at time point D (FIG. 2D) the gates P3 and P4 are biased on. Charge is transferred from the P1 storage well to the P3 storage well during a time that the P4 transfer gate is inhibiting transfer and is off, and the P2 and P3 gates are biased on. At the time the P1 gate transitions off, the P3 gate transitions on thereby extending the depleted MOS region from the P1 gate and through the P3 gate. Charge previously introduced into the P1 well is partitioned between the P1, P2 and P3 gates at this time. While the P2 and P3 gates are biased, the P1 gate clocks off, and charge under the P1 gate flows to the P2 and P3 depletion regions. The P2 gate is then clocked off, moving all of the charge to the P3 charge storage well. This process results in moving the charge from the P1 charge well to the P3 charge well. In a similar manner charge can be moved from the P3 charge well to the next P1 charge well.
The CCD structure offers a number of advantages. For example, the CCD structure makes very efficient utilization of available silicon integrated circuit real-estate for charge storage capacity. Since the CCD is normally operated as a complete charge transfer device, very high charge transfer efficiencies and low noise levels are achieved. However, the requirements for the manufacturing process to support an active poly-2 transistor, with the ability to form active devices crossing the overlapping boundary for the poly-1 and poly-2 structures, requires specialized processing that is not generally available in modern sub-micron commercial CMOS technology.
FIG. 3 and FIGS. 4A and 4B (collectively referred to as FIG. 4) illustrate the timing and schematic diagrams, respectively, for a conventional 2-phase bucket brigade structure. FIG. 4 illustrates a single poly implementation for the bucket brigade structure, which is assumed to be P-channel. FIG. 4A illustrates the two phase bucket brigade at timing condition "A" as illustrated in FIG. 3, while FIG. 4B illustrates the two phase bucket brigade at timing condition "B" as illustrated in FIG. 3. Sources for each transfer well are shown to the left side of each phase, P1 and P2, with a depletion implant (DI) covering most of the active area of each phase and forming the drain. For this type of device the charge is stored in the potential of the depletion implant.
Referring to FIG. 4A, at this time the bucket brigade gate P1 is clocked on, thereby lowering the potential of the MOS surface at the source of the charge well. This process also lowers the potential of the depletion implant and drain for the well. The potential of the gate P2 is raised at this time causing charge stored under P2 in the depletion implant to spill over the potential barrier established by the surface potential under the P1 gate and into the potential of the depletion implant under P1. This acts to raise the potential of the depletion implant located under P1 above the potential previously established by the P2 gate transfer barrier. The additional potential in the P1 depletion implant will then source the transfer charge to the P2 well in the subsequent transfer, as illustrated by timing condition "B" shown in FIG. 4B.
While relatively simple, the conventional bucket brigade structure suffers from a number of performance limitations. One primary limitation is that the principal charge storage well in the structure, the depletion implant, contributes kTC noise. As a consequence there is a direct relationship between the well capacity and the noise performance that can be achieved in the device. Furthermore, since the charge transfer process relies on a diffusion for supplying charge over a MOS barrier, the charge transfer process is incomplete, which presents limitations on the device charge transfer efficiency performance. In addition, the conventional bucket brigade fabrication process, while requiring only a single poly-process, also requires a depletion implant option. However, a depletion implant option for submicron CMOS processes is not readily available at many foundries.